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74F219 64-Bit Random Access Memory with 3-STATE Outputs
June 1988 Revised July 1999
74F219 64-Bit Random Access Memory with 3-STATE Outputs
General Description
The 74F219 is a high-speed 64-bit RAM organized as a 16word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs are 3-STATE and are in the high-impedance state whenever the Chip Select (CS) input is HIGH. The outputs are active only in the Read mode. This device is similar to the 74F189 but features non-inverting, rather than inverting, data outputs.
Features
s 3-STATE outputs for data bus applications s Buffered inputs minimize loading s Address decoding on-chip s Diode clamped inputs minimize ringing s Available in SOIC (300 mil only)
Ordering Code:
Order Number 74F219SC 74F219SJ 74F219PC Package Number M16B M16D N16E Package Description 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
(c) 1999 Fairchild Semiconductor Corporation
DS009500
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74F219
Unit Loading/Fan Out
Pin Names A0-A3 CS WE D0-D3 O0-O3 Description Address Inputs Chip Select Input (Active LOW) Write Enable Input (Active LOW) Data Inputs 3-STATE Data Outputs U.L. HIGH/LOW 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 150/40 (33.3) Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-1.2 mA 20 A/-0.6 mA 20 A/-0.6 mA -3 mA/24 mA (20 mA)
Function Table
Inputs Operation CS L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Condition of Outputs High Impedance True Stored Data High Impedance
WE L H X Write Read Inhibit
Block Diagram
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74F219
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI ICEX VID IOD IIL Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current IOZH IOZL IOS IZZ ICC Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current 37 -60 4.75 3.75 -0.6 -1.2 50 -50 -150 500 55 A A mA A mA Max Max Max 0.0V Max 10% VCC 2.5 2.4 2.7 2.7 0.5 5.0 7.0 50 V A A A V A mA Min Max Max Max 0.0 0.0 Max V Min Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -3 mA IOH = -1 mA IOH = -3 mA IOL = 24 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (An, WE, Dn) VIN = 0.5V (CS) VOUT = 2.7V VOUT = 0.5V VOUT = 0V VOUT = 5.25V
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74F219
AC Electrical Characteristics
TA = +25C Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Access Time, HIGH or LOW An to On Access Time, HIGH or LOW CS to On Disable Time, HIGH or LOW CS to On Write Recovery Time HIGH or LOW, WE to On Disable Time, HIGH or LOW WE to On 10.0 8.0 3.5 5.0 2.0 3.0 6.5 6.5 4.0 5.0 VCC = +5.0V CL = 50 pF Typ 18.5 13.5 6.0 9.0 4.0 5.5 20.0 11.0 7.0 9.0 Max 26.0 19.0 8.5 13.0 6.0 8.0 28.0 15.5 10.0 13.0 TA = -55C to +125C VCC = +5.0V CL = 50 pF Min 9.0 8.0 3.5 5.0 2.0 2.5 6.5 6.5 3.5 5.0 Max 32.0 23.0 10.5 15.0 8.0 10.0 37.5 17.5 12.0 15.0 TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 10.0 8.0 3.5 5.0 2.0 3.0 6.5 6.5 4.0 5.0 Max 27.0 20.0 9.5 14.0 7.0 9.0 29.0 16.5 11.0 14.0 ns ns ns Units
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(L) tH(L) Setup Time, HIGH or LOW An to WE Hold Time, HIGH or LOW An to WE Setup Time, HIGH or LOW Dn to WE Hold Time, HIGH or LOW Dn to WE Setup Time, LOW CS to WE Hold Time, LOW CS to WE tW(L) WE Pulse Width, LOW 6.0 15.0 6.0 ns 6.0 7.5 6.0 0 0 2.0 2.0 10.0 10.0 0 0 0 Max TA = -55C to +125C VCC = +5.0V Min 0 0 2.0 2.0 11.0 11.0 2.0 2.0 0 Max TA = 0C to +70C VCC = +5.0V Min 0 0 2.0 2.0 10.0 10.0 0 0 0 ns ns Max ns Units
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74F219
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M16B
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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74F219 64-Bit Random Access Memory with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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